This invention relates to MOS circuits and more particularly to improvements therein.
A commonly used circuit arrangement for MOS circuits is one wherein operating current or leakage current is supplied through an MOSFET or other semiconductor devices which are connected so that the current which meets the requirements of the load can pass therethrough. If the load is capacitive, as it usually is, then it is found that the turn on time or rise time of the circuit is usually very much shorter than its turn off time. In other words the recovery time of the circuit is very much longer than its turn on time.
It should be obvious that the speed with which the circuit can be used repetitively is determined by the time required to turn it on and turn it off. For example, if the load is a semiconductor memory, then the cycle time for reading and writing is definitely affected by the time required for the memory system to return to equilibrium after an operation. Accordingly, any arrangement which shortens the recovery time required for such a circuit would improve the rapidity at which circuits of the type indicated can be used.